In addition to frequency synchronization, the main role of most phase locked loops (PLLs) is phase alignment. Any type II PLL (e.g. a PLL having two integrators in the loop) should be capable of maintaining phase alignment between its selected reference clock and output clocks to a certain limit. The delay variation of the reference clock and output clock pins, as well as the interconnection lines, limits the alignment accuracy. For applications that are sensitive to such alignment variations, i.e. for applications that require accurate alignment to be maintained over process, voltage and temperature variations, different compensation mechanisms have been provided. A prior art solution for maintaining alignment accuracy is the use of external feedback as shown in FIG. 1.
An important disadvantage of the prior art is the lack of flexibility as a result of the expensive resources needed to support proper alignment. To be able to independently control the alignment of each output, the prior art solution would require as many external feedback connections as the number of output clocks, or at least as the number of output pin types. Each external feedback connection requires its own reference sampling module and PLL, as well as independent input and output pins. This would be very expensive, and in most cases the practical prior art solution is to provide only a single external feedback connection. The lack of a separate external feedback connection for each output clock limits the alignment accuracy that can be maintained due to different loading per output clock and the delay changes caused by voltage and temperature variations.
It is also important to note the technical difficulty, or inability, of the prior art solutions to maintain proper alignment among different types of output pins (single ended vs. differential) due to the different delay variation over voltage and temperature unless each output has its own feedback line.